Adder Circuit | Research & Encyclopedia Articles

Adder Circuit

The adder is the most basic computational element of a computer. All other arithmetic computations are based on adding. Subtraction, for example, is accomplished by adding two properly formatted numbers (two's complement being a common format), while multiplication and division are implemented as repeated additions and subtractions, respectively. If the central processing unit (CPU) is the heart of the computer, the adder is the heart of the CPU.

Computer hardware works with binary numbers, which are strings of single binary digits (bits, 1s and 0s). To build a binary adder of any size it is sufficient to build a unit which can add two single bits--and this is not difficult, for in single-bit addition there are only three calculations that can be performed:

• 0 + 0 = 0
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• 0 + 1 = 0
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• 1 + 1 = 10

In the third case we encounter a slight complication: A single bit of output does not suffice to represent the sum of 1 and 1, and we must "carry" a 1 to the next place. A 1-bit adder, therefore, must accept two bits of input (the bits to be added) and generate two bits of output. These two bits can be designated the SUM bit and the CARRY OUT bit. In the case of "1 + 1 = 10," SUM = 0 and CARRY OUT = 1.

If the goal were to specify the input-output behavior of a single-bit adder, the design process could stop right here. But if the goal is to create a 1-bit adder that can be chained with N - 1 identical fellow units to form a device that adds two N-bit numbers--and that is the goal--a few more steps are necessary. For if each 1-bit adder generates a CARRY OUT bit, the next adder in line must accept this carry signal as an input--call it a CARRY IN bit--and handle it correctly. The rules for handling carries in binary addition are basically the same as those for carrying digits in ordinary decimal addition such as we all learn in grade school. The table below is a complete input/output specification for a single, chainable 1-bit adder. (In the table, A stands for one 1-bit addend and B for the other.)

A circuit producing these results can be built utilizing 11 logic gates (4 AND gates, 5 OR gates, and 2 NOT gates or "inverters"). N of these 1-bit adder circuits can be wired in a row to produce an N-bit adder (i.e., an adder that accepts two N-bit numbers simultaneously). The procedure for making the N-bit adder from N 1-bit adders is as follows: (1) The rightmost (least significant) bit of both addends is fed into the rightmost 1-bit adder, the bit to the left of that is fed into the next adder to the left, and so on for all N bits. (2) Since the least-significant digit never receives a carry (there is no digit to the right of it to generate a carry), the first 1-bit adder's CARRY IN input can be tied (hardwired) to 0. (3) The first 1-bit adder's CARRY OUT is wired to the CARRY IN of the second one, the CARRY OUT of the second is wired to the CARRY IN of the third, and so on through all N adders. (4) The lined-up SUM bits of the N 1-bit adders give the N-bit sum of the two N-bit addends.

The CARRY OUT bit of the most significant (leftmost) 1-bit adder serves as an OVERFLOW indicator--a signal that an addition has been attempted which results in a number too large to represent with N bits. This is not a design flaw in this adder, for no matter how much memory is built into a computer there will be some number that is the largest it can represent.