In the x86 assembly language, the TEST instruction performs a bitwise AND on two operands. The flags SF, ZF, PF, CF, OF and AF are modified while the result of the AND is discarded. There are 9 different opcodes for the TEST instruction depending on the type and size of the operands. It can compare 8bit, 16bit or 32bit values. It can also compare registers, immediate values and register indirect values.[1]
TEST opcode variations
| Opcode | Instruction |
|---|---|
| A8 lb | TEST AL,imm8 |
| A9 lw | TEST AX,imm16 |
| A9 ld | TEST EAX,imm32 |
| F6 /0 lb | TEST r/m8,imm8 |
| F7 /0 lw | TEST r/m16,imm16 |
| F7 /0 ld | TEST r/m32,imm32 |
| 84 /r | TEST r/m8,r8 |
| 85 /r | TEST r/m16,r16 |
| 85 /r | TEST r/m32,r32 |
The TEST operation sets the flags CF and OF to zero. The SF is set to the MSB of the result of the AND. If the result of the AND is 0, the ZF is set to 1, otherwise set to 0. The parity flag is set to the bitwise XNOR of the result of the AND. The value of AF is undefined.
References
- ^ Intel Architecture Software Developer's Manual, Volume 2: Instruction Set Reference Manual (PDF). Retrieved on 2007-10-25.
