This article is about the Intel microarchitecture. For Intel processors branded as "Intel Core", such as the 65-nanometre processor codenamed Yonah and its variants, which does not use the Intel Core microarchitecture, despite its name, see Intel Core. For the line of "Intel Core 2" processors using the Intel Core microarchitecture, see Intel Core 2.
The Intel Core microarchitecture (previously known as the Intel Next-Generation Micro-Architecture, or NGMA) is a multi-core processormicroarchitecture unveiled by Intel in Q1 2006. It is based around an updated version of the Yonah core and could be considered the latest iteration of the Intel P6 microarchitecture, which traces its history back to the 1995Pentium Pro. The extreme power consumption of NetBurst-based processors and the resulting inability to effectively increase clock speed was the primary reason Intel abandoned the NetBurst architecture. The Intel Core Microarchitecture was designed by the Intel Israel (IDC) team that previously designed the Pentium M mobile processor. The architecture features lower power usage than before and is competitive with AMD in heat production. It has multiple cores and hardware virtualization support (marketed as Virtualization Technology), as well as Intel 64 (Intel's implementation of x86-64) and SSSE3. The first processors that used this architecture were code-named Merom, Conroe, and Woodcrest; Merom is for mobile computing, Conroe is for desktop systems, and Woodcrest is for servers and workstations. While architecturally identical, the three processor lines differ in the socket used, bus speed, and power consumption. Low-end Core-based processors are branded Pentium Dual Core and Celeron; server and workstation Core-based processors are branded Xeon, while desktop and mobile Core-based processors are branded as Core 2. The Intel Core processors do not use the Core microarchitecture.
Intel CPU core roadmaps from NetBurst and Pentium M to Sandy Bridge. The Core family of processors are those with the light green background.
The Intel Core Microarchitecture is designed from the ground up, but similar to the Pentium M microarchitecture in design philosophy. The pipeline is 14 stages long — less than half of Prescott's, a signature feature of wide order execution cores. Core's execution unit is 4-issues wide, compared to the 3-issue cores of P6, P-M (Banias, Dothan, and Yonah), and NetBurst microarchitectures. The new architecture is a dual core design with linked L1 cache and shared L2 cache engineered for maximum performance per watt and improved scalability. One new technology included in the design is Macro-Ops Fusion, which combines two x86 instructions into a single micro-operation. For example, a common code sequence like a compare followed by a conditional jump would become a single micro-op. Other new technologies include 1 cycle throughput (2 cycles previously) of all 128-bit SSE instructions and a new power saving design. All components will run at minimum speed, ramping up speed dynamically as needed (similar to AMD's Cool'n'Quiet power-saving technology, as well as Intel's own SpeedStep technology from earlier mobile processors). This allows the chip to produce less heat, and consume as little power as possible. For Woodcrest, the server and workstation variant, the front side bus (FSB) runs at 1333 MT/s for most Woodcrest CPUs and 1066 MT/s for the 1.60 and 1.86 GHz Woodcrest processors[1][2]. It is targeted to run at 667 MT/s for Merom, the mobile variant. The second wave of Meroms, supporting 800 MT/s FSB, have been released on a different socket in May 2007. The desktop version is officially slated to use the 1066 MT/s bus, with a 1333 MT/s bus line officially launching on July 22nd, and a budget version with an 800 MT/s FSB, but that would be slightly more limited due to its more restrictive bus. In 2007, AMD released a series of videos claiming that the FSB will prove to be the weak link for Intel, as the Core microarchitecture uses a shared bus, unlike their own HyperTransport. While not so critical in the mobile and desktop segments, this might be the handicap which will prevent Woodcrest-MP from taking the performance lead from AMD Opteron on systems with more than 2 cores per socket. Intel attempted to alleviate this problem by the use of advanced prefetchers and memory disambiguation which try to hide main-memory-access latency. However, this is mitigated to some degree by the use of a separate front-side bus for each physical CPU package. The power consumption of these new processors is extremely low — average use energy consumption is to be in the 1-2 watt range in ultra low voltage variants, with Thermal Design Powers (TDPs) of 65 watts for Conroe and most Woodcrests, 80 watts for the 3.0 GHz Woodcrest, and 40 watts for the low-voltage Woodcrest. However, this is subject to change. In comparison, an AMD Opteron 875HE processor consumes 55 watts, while the new Energy Efficient Socket AM2 line fits in the 35 watt thermal envelope (specified a different way so not directly comparable). Merom, the mobile variant, is listed at 35 watts Thermal Design Power (TDP) for standard versions and 5 watts TDP for Ultra Low Voltage (ULV) versions. Previously, Intel warned that it would now focus on power efficiency, rather than raw performance. However, at IDF in the spring of 2006, Intel advertised both. Some of the promised numbers are:
20% more performance for Merom at the same power level (compared to Core Duo)
40% more performance for Conroe at 40% less power (compared to Pentium D)
80% more performance for Woodcrest at 35% less power (compared to the original dual-core Xeon)
This section contains information about scheduled or expected future computer chips.
It may contain preliminary or speculative information, and may not reflect the final specification of the product.
