In digital signal processing, a digital down-converter (DDC) converts a digitized real signal centered at an intermediate frequency (IF) to a basebanded complex signal centered at zero frequency. In addition to downconversion, DDC’s typically decimate to a lower sampling rate, allowing follow-on signal processing by lower speed processors.
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Architecture
A DDC consists of three subcomponents; a Direct Digital Synthesizer (DDS) which generates a complex sinusoid at the intermediate frequency, a pair of multipliers to convert (in quadrature) from IF to baseband, and a pair of lowpass filters and decimators. The multipliers perform the downconversion function, but in addition to downconverting by creating a difference signal at the IF minus the DDS frequency, they also upconvert, generating an unwanted signal at the sum of the two frequencies. The lowpass filters pass only the desired signal and also perform anti-alias filtering prior to decimation. Any suitable lowpass filter can be used including FIR, IIR and CIC filters. The most common choice is a FIR filter for low amounts of decimation (less than ten) or a CIC filter followed by a FIR filter for larger downsampling ratios.
Variations on the DDC
Several variations on the DDC are useful, including many that input a feedback signal into the DDS. These include:
- Decision directed carrier recovery phase locked loops in which the I and Q are compared to the nearest ideal constellation point of a PSK signal, and the resulting error signal is filtered and fed back into the DDS
- A Costas loop in which the I and Q are multiplied and low pass filtered as part of a BPSK/QPSK carrier recovery loop
Implementation
DDC’s are most commonly implemented in logic in field-programmable gate arrays or application-specific integrated circuits. While software implementations are also possible, operations in the DDS, multipliers and input stages of the lowpass filters all run at the sampling rate of the input data. This data is commonly taken directly from analog to digital converters (ADC’s) sampling at tens or hundreds of MHz, which is beyond the real time computational capabilities of software processors.
