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Cycles Per Instruction

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In computer architecture, Cycles per instruction (clock cycles per instruction or clocks per instruction or CPI) is a term used to describe one aspect of a processor's performance: the number of clock cycles that happen when an instruction is being executed. It is the multiplicative inverse of Instructions Per Cycle.

Let us assume a Classic RISC pipeline, with the following 5 stages:

1) Instruction fetch cycle (IF)
2) Instruction decode cycle (ID)
3) Execution cycle (EX)
4) Memory access (MEM)
5) Write-back cycle (WB)

Each stage requires one clock cycle and an instruction passes through the stages sequentially. Without Pipelining, a new instruction is fetched in stage 1 only after the previous instruction finishes at stage 5. Therefore without pipelining the number of cycles it takes to execute an instruction is 5. This is the definition of CPI. With pipelining we can improve the CPI by exploiting Instruction level parallelism. For example, what if an instruction is fetched every cycle? We could theoretically have 5 instructions in the 5 stage pipeline at once (one instruction per stage). In this case, a different instruction would complete stage 5 in every clock cycle, and therefore on average we have one clock cycle per instruction (CPI = 1). With a single issue processor, the best CPI attainable is 1. However with multiple issue processors, we may achieve even better CPI values. For example a processor that issues two instruction per clock clock (see Superscalar processors) can achieve a CPI of 0.5 when two instructions are completing every clock cycle.