Bus Functional Model or BFM is a non-synthesizable software model of an integrated circuit component. This software model can be used to simulate the behavior of a hardware system before building and testing the actual hardware. BFM are typical written in HDL's languages such as verilog, HDL, or SystemC. BFM's are often used as reusable building blocks for create simulation testbenches, where the signal ports on a design under test are connected to the appropriate BFM's in the testbench for the purpose of simulation.
Transaction Verification Models
BFM's are some times referred to as TVM's or Transaction verification models. This is to emphasize that bus operations of the model have have been bundled into atomic bus transactions to make it easier to issue and view bus transactions. Viewing of bus transactions of TVMs is similar to viewing the output of a protocol analyzers or bus sniffer.
